The present application relates generally to semiconductor devices, and more specifically to methods for manufacturing fin field effect transistors.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
The gate structure may be formed using a gate-first or a gate-last fabrication process. A gate-last process, such as a replacement metal gate (RMG) process, utilizes a sacrificial or dummy gate, which is replaced by a functional gate after device activation, i.e., after dopant implantation into source/drain regions of the fins and an associated drive-in anneal, in order to avoid exposing the functional gate materials to the thermal budget associated with activation.
A “functional gate” refers to a structure used to control output current (i.e., the flow of carriers through a channel) of a semiconductor device using an electrical field or, in some instances, a magnetic field. A functional gate typically includes one or more gate dielectric layers and one or more gate conductor layers.
Prior to removing the sacrificial gate and forming a functional gate, a gate cut module may be used to sever (i.e., segment) the sacrificial gate in order to define and isolate adjacent devices. In association with such a process, portions of the sacrificial gate are removed to form openings that are backfilled with an etch selective dielectric material, i.e., isolation layer, that provides a barrier between adjacent functional gates following removal and replacement of the remaining sacrificial gate material.
At advanced nodes, however, notwithstanding recent developments, it remains a challenge to define a gate cut opening with both the desired critical dimensions and alignment precision amidst a plurality of densely-arrayed fins. For instance, the formation of a gate cut opening typically involves the competing objectives of thoroughly removing sacrificial gate material from within the opening, while not compromising a critical dimension of the opening due to excessive etching.
Notably, an insufficient etch and the incomplete removal of the sacrificial gate material, especially at the bottom of the gate cut opening, may result in a short circuit between later-formed functional gates. On the other hand, an over-etch to ensure complete removal of the sacrificial gate material may increase a critical dimension of the gate cut opening and correspondingly decrease the gap between the isolation layer and an adjacent fin. As the gap between the isolation layer and an adjacent fin decreases, it is increasingly challenging to remove material such as an extended gate oxide from the fin without leaving unwanted residue. It is also a processing challenge to deposit a complete functional gate into an overly narrow gap.